The author's more recent work is here:

http://arc.cecs.pdx.edu/publications

Related talk by the author (Ivan Sutherland): https://www.youtube.com/watch?v=jR9pAaQlVRc

When I read the title I was reminded of this

https://youtu.be/tVT2Xi1kwx0

in verilog there is a distinction between asynchronous combinatorial logic and synchronous sequential logic

wires are treated as transmission lines