So the node scaling was standardized (before ~28nm). It very literally meant MOSfet density (as 28 nm was 1 MOSfet + gap for the next MOSfet). The IEEE had a road map about what to expect out of X sized components, and when those components would be out base on historical data.

But when we hit 20/18/16/14nm that went out the window and it became a marketing term, not so much a literal description. A lot of this was driven by moving to FINfet's which are really MOSfets, as they have lower leakage at smaller sizes, but they also aren't square which makes generalizing a singular node to density a bit wonky.

Yea for consumers these days, the physical size really doesn't matter much at all. ICs are small enough, nobody's looking forward to 5nm because of the physical size. What matters is cost and electric power usage.

The density improvements from 5nm absolutely matter and that comes from being smaller. If I can fit the functionality from two chips on one chip I save significant space on my board. Especially if the size of my chip is defined by the beachfront available for escaping IO. Not to mention all the supporting components required for each chip. And with half the chip turned off I can finally handle the power/heat issues.

We care about the TDP, which can be improved in various ways, not just moving to 5nm. Physical size in a phone or whatever is small enough, we don't care about smaller chips. The amount of space saved is negligible.

It's never been just about phones. These chips go into all kinds of products, some of them with real thermal and size restrictions.

TDP = thermals, which I did mention. You can reduce thermals in other ways, not just smaller features.

Size is small enough for anything consumers care about, even watches.

> Only thing that matters is waffer price, yield, transistor count and TDP.

Wouldn't 5 nm allow shorter wire traces, which would reduce another limiting factor in computational speed?

Not really.

The fundamental limit of clock speed is power draw. As clocks increase the wattage ~ frequency relation goes from

     frequency = Constant * Power Draw

It starts becoming

     frequency = Power Draw * Power Draw

As you start getting >3GHz so while we can make processors that run >5GHz. There just aren't applications that benefit a lot from it.

I think you have that backwards, unless you mean to say the the power draw is proportionate to the square root of frequency at higher clocks.

Well, you can fight the power monster with dark silicon.

Packing things in more tightly lets you spend less time in transit, which might let you squeeze more gates into a cycle, or do the same things a little faster.