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A datasheet for a related non-power-of-2-sized product from Micron gives a hint as to what they're doing:

https://prod.micron.com/~/media/documents/products/data-shee...

Page 28:

"For non-binary memory densities, only a half of the row address space is valid. When the MSB address bit is HIGH, then the MSB-1 address bit must be LOW."

They basically cut off the upper 1/4 of the address decoder.



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