We are not disagreeing with the "386SX is to 386[DX] as 8088 is to 8086" part, or the effect on memory bandwidth.
But the "386SX was a 16-bit CPU capable of 32-bit operations" is simply an incorrect statement, which we are correcting. The 386SX was a 32-bit CPU with a 16-bit data bus.
Your new Z80 comparison seems flawed too: while it supports some 16-bit operations over paired 8-bit registers, including 16-bit load & save, the Z80 is generally considered to be an 8-bit CPU (so it is an 8-bit CPU capable of 16-bit operations) and in any case it has an 8-bit data bus (see the diagram in https://www.petervis.com/electronics/CPU_Processors/Zilog_Z8..., note that there are only 8 data lines, D0 through D7) so it can't pull/push 16-bits at once externally any more than the 8088 can.
Okay. From an architecture point of view, I agree with you. The context of my post related to the databus width and the speed implications of it. Sorry I wasn't clear in my meaning.
But the "386SX was a 16-bit CPU capable of 32-bit operations" is simply an incorrect statement, which we are correcting. The 386SX was a 32-bit CPU with a 16-bit data bus.
Your new Z80 comparison seems flawed too: while it supports some 16-bit operations over paired 8-bit registers, including 16-bit load & save, the Z80 is generally considered to be an 8-bit CPU (so it is an 8-bit CPU capable of 16-bit operations) and in any case it has an 8-bit data bus (see the diagram in https://www.petervis.com/electronics/CPU_Processors/Zilog_Z8..., note that there are only 8 data lines, D0 through D7) so it can't pull/push 16-bits at once externally any more than the 8088 can.