Great document for those with an interest in PowerPC assembly and still generally applicable to modern Power ISA. Some of these code sections appear in the TenFourFox JIT to this day.
I tried to see if this doc had anything about calling conventions for 64b parameters on 32b ILP32, but alas...(at least a cursory skim of `A.1 Procedure Interfaces` came up empty).
Another fun fact I learned about PPC assembly for that bug is that without `-mregnames`, it can be hard to distinguish between registers and constants in compiler generated PPC assembly. Official docs from IBM (https://developer.ibm.com/technologies/linux/articles/l-ppc/) say "Get used to it. :)" LOL
For 32-bit PowerPC, PowerOpen is the ABI used in PPC Mac OS and OS X (largely, with a couple minor differences) and AIX. The System V ABI is pretty much everything else, but it's really a misnomer since the *BSDs on 32-bit PowerPC use SysV too.
Yes, I regret it as well, but even getting Classilla to TLS 1.1 would be a big deal, and 1.2 (let alone 1.3) would require a lot of rewriting. $DAYJOB is crazy at the moment, and keeping TenFourFox up with Mozilla's monthly release cadence is taking time away from me doing more Power ISA work on mainline Firefox for the Talos II I'm typing this on (let alone other fun projects I'd like to get to). Classilla just loses out because of the amount of work needed to fix it and the very small amount of cycles I have available.
This 16-core (2x8) Talos II is around $8ish-K, which is still a lot, but I feel I got my money's worth out of it. 64 threads is good times (each core is SMT-4). I run a "stripper" spec for the Blackbird, which was an experiment to see how low it could go; it came to around $2100, but I would advise going a little higher spec than I did (single-4, no GPU).
The T2 is a great machine, though. There's just no comparison to the Quad G5 sitting next to it. It's quieter, it uses less power and it doesn't feel like I'm lacking for CPU. I got a lot of wear out of the G5 and I'll never get rid of it, but if you don't need 32-bit and/or to run OS X on the metal, the best Power workstation is a Raptor.
...
Xilinx introduced Virtex-II family in January 2001 on 150 nm process technology,[14] and Virtex-II Pro family in March 2002 on 130 nm process technology.
Aaaah, the Power ISA... If you want to "rotate left immediate speculatively if condition matches additionally push sign bit on the stack and zero extend the next register unless it has an odd value", this is the most likely architecture to do that for you ;-) At least its the one I most often need to take a look at the manual what slxwimzus (or something like that) exactly does when looking at disassembly. Of course luckily most compilers don't do the freaky stuff, so I'm probably quite lucky :)
"IBM has a well-known disdain for vowels, and basically refuses to use them for mnemonics (they were called on this, and did "eieio" as an instruction just to try to make up for it)."
A common misunderstanding of the phrase "reduced instruction set computer" is the mistaken idea that instructions are simply eliminated, resulting in a smaller set of instructions.[2] In fact, over the years, RISC instruction sets have grown in size, and today many of them have a larger set of instructions than many CISC CPUs.
[Snip]
The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing.[citation needed]
The term load/store architecture is sometimes preferred.
This is a great book that is good to see preserved and available in PDF form. A lot of this is applicable to other architectures, and gives a good view into how compiler engineers think..
Henry Warren, the author of Hacker’s Delight[0], is one of the authors of this book.
Chapters 3, 5, and Appendix D have some neat examples of bit twiddling code in Power assembly language.
The content overlaps with that of Hacker’s Delight and Bit Twiddling Hacks[1].
[0] https://en.wikipedia.org/wiki/Hacker%27s_Delight
[1] https://graphics.stanford.edu/~seander/bithacks.html