Do you have a reference on that? This summary of the Alpha AXP <https://danluu.com/dick-sites-alpha-axp-architecture.pdf> states "Normal load or store instructions that specify
an unaligned address take a precise data alignment trap to PALcode (which may do the access using two aligned accesses or report a fatal error, depending on the operating system design)"
Thanks for the PDF, nice when somebody provides more than the minimum information. Okay, from the same doc:
The integer load and store quadword unaligned
(LDQ_U, STQ_U) instructions ignore the low three
bits of the byte address and always transfer an
aligned quadword
So sort of right, if you squint and don't look too closely :-)
(edit: oh, you're the author? Didn't realise. Good stuff)
